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Fix T101438: Wrong LOD selection after clamping the mip value (Nvidia)
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Authored by Miguel Pozo (pragma37) on Oct 2 2022, 6:04 PM.

Details

Summary

Fix for T101438

Clamping the mip seems to always set it to 9.0.
I couldn't find an alternative way to avoid triggering the error (ie. min(mip, 9.0)).

In any case, the results with this patch applied look the same to the (correct) ones on AMD.
And, since clamping the max mip to a hardcoded value could result in resolution-depended behavior, I guess disabling the clamp should be ok anyway.

Diff Detail

Repository
rB Blender
Branch
master
Build Status
Buildable 24070
Build 24070: arc lint + arc unit

Event Timeline

Miguel Pozo (pragma37) requested review of this revision.Oct 2 2022, 6:04 PM
Miguel Pozo (pragma37) created this revision.
Miguel Pozo (pragma37) edited the summary of this revision. (Show Details)Oct 2 2022, 6:07 PM

The clamp was introduced because the mip levels might have been specified (allocated) but not populated correctly. But I guess if the sampler mip range is correct (contains the updated downsampled mips), this patch should be ok.

We can commit it as is and remove the comment. I don't even know why the 9 was here since MAX_SCREEN_BUFFERS_LOD_LEVEL is 6. The downsample step should be setting the sampler mip limits accordingly.

This revision is now accepted and ready to land.Oct 3 2022, 3:46 PM