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intern/cycles/util/util_system.cpp
| Show All 9 Lines | |||||
| * Unless required by applicable law or agreed to in writing, software | * Unless required by applicable law or agreed to in writing, software | ||||
| * distributed under the License is distributed on an "AS IS" BASIS, | * distributed under the License is distributed on an "AS IS" BASIS, | ||||
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||||
| * See the License for the specific language governing permissions and | * See the License for the specific language governing permissions and | ||||
| * limitations under the License. | * limitations under the License. | ||||
| */ | */ | ||||
| #include "util_system.h" | #include "util_system.h" | ||||
| #include "util_debug.h" | |||||
| #include "util_types.h" | #include "util_types.h" | ||||
| #include "util_string.h" | #include "util_string.h" | ||||
| #ifdef _WIN32 | #ifdef _WIN32 | ||||
| #if(!defined(FREE_WINDOWS)) | #if(!defined(FREE_WINDOWS)) | ||||
| #include <intrin.h> | #include <intrin.h> | ||||
| #endif | #endif | ||||
| #include <windows.h> | #include <windows.h> | ||||
| ▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines | struct CPUCapabilities { | ||||
| bool avx2; | bool avx2; | ||||
| bool xop; | bool xop; | ||||
| bool fma3; | bool fma3; | ||||
| bool fma4; | bool fma4; | ||||
| bool bmi1; | bool bmi1; | ||||
| bool bmi2; | bool bmi2; | ||||
| }; | }; | ||||
| static void system_cpu_capabilities_override(CPUCapabilities *caps) | |||||
| { | |||||
| /* Only capabilities which affects on cycles kernel. */ | |||||
| if(getenv("CYCLES_CPU_NO_AVX2")) { | |||||
| caps->avx2 = false; | |||||
| } | |||||
| if(getenv("CYCLES_CPU_NO_AVX")) { | |||||
| caps->avx = false; | |||||
| } | |||||
| if(getenv("CYCLES_CPU_NO_SSE41")) { | |||||
| caps->sse41 = false; | |||||
| } | |||||
| if(getenv("CYCLES_CPU_NO_SSE3")) { | |||||
| caps->sse3 = false; | |||||
| } | |||||
| if(getenv("CYCLES_CPU_NO_SSE2")) { | |||||
| caps->sse2 = false; | |||||
| } | |||||
| if(getenv("CYCLES_CPU_NO_SSE")) { | |||||
| caps->sse = false; | |||||
| } | |||||
| } | |||||
| static CPUCapabilities& system_cpu_capabilities() | static CPUCapabilities& system_cpu_capabilities() | ||||
| { | { | ||||
| static CPUCapabilities caps; | static CPUCapabilities caps; | ||||
| static bool caps_init = false; | static bool caps_init = false; | ||||
| if(!caps_init) { | if(!caps_init) { | ||||
| int result[4], num; | int result[4], num; | ||||
| Show All 36 Lines | #endif | ||||
| caps.f16c = (result[2] & ((int)1 << 29)) != 0; | caps.f16c = (result[2] & ((int)1 << 29)) != 0; | ||||
| __cpuid(result, 0x00000007); | __cpuid(result, 0x00000007); | ||||
| caps.bmi1 = (result[1] & ((int)1 << 3)) != 0; | caps.bmi1 = (result[1] & ((int)1 << 3)) != 0; | ||||
| caps.bmi2 = (result[1] & ((int)1 << 8)) != 0; | caps.bmi2 = (result[1] & ((int)1 << 8)) != 0; | ||||
| caps.avx2 = (result[1] & ((int)1 << 5)) != 0; | caps.avx2 = (result[1] & ((int)1 << 5)) != 0; | ||||
| } | } | ||||
| system_cpu_capabilities_override(&caps); | |||||
| caps_init = true; | caps_init = true; | ||||
| } | } | ||||
| return caps; | return caps; | ||||
| } | } | ||||
| bool system_cpu_support_sse2() | bool system_cpu_support_sse2() | ||||
| { | { | ||||
| CPUCapabilities& caps = system_cpu_capabilities(); | CPUCapabilities& caps = system_cpu_capabilities(); | ||||
| return caps.sse && caps.sse2; | return DebugFlags().cpu.sse2 && caps.sse && caps.sse2; | ||||
| } | } | ||||
| bool system_cpu_support_sse3() | bool system_cpu_support_sse3() | ||||
| { | { | ||||
| CPUCapabilities& caps = system_cpu_capabilities(); | CPUCapabilities& caps = system_cpu_capabilities(); | ||||
| return caps.sse && caps.sse2 && caps.sse3 && caps.ssse3; | return DebugFlags().cpu.sse3 && | ||||
| caps.sse && caps.sse2 && caps.sse3 && caps.ssse3; | |||||
| } | } | ||||
| bool system_cpu_support_sse41() | bool system_cpu_support_sse41() | ||||
| { | { | ||||
| CPUCapabilities& caps = system_cpu_capabilities(); | CPUCapabilities& caps = system_cpu_capabilities(); | ||||
| return caps.sse && caps.sse2 && caps.sse3 && caps.ssse3 && caps.sse41; | return DebugFlags().cpu.sse41 && | ||||
| caps.sse && caps.sse2 && caps.sse3 && caps.ssse3 && caps.sse41; | |||||
| } | } | ||||
| bool system_cpu_support_avx() | bool system_cpu_support_avx() | ||||
| { | { | ||||
| CPUCapabilities& caps = system_cpu_capabilities(); | CPUCapabilities& caps = system_cpu_capabilities(); | ||||
| return caps.sse && caps.sse2 && caps.sse3 && caps.ssse3 && caps.sse41 && caps.avx; | return DebugFlags().cpu.avx && | ||||
| caps.sse && caps.sse2 && caps.sse3 && caps.ssse3 && caps.sse41 && caps.avx; | |||||
| } | } | ||||
| bool system_cpu_support_avx2() | bool system_cpu_support_avx2() | ||||
| { | { | ||||
| CPUCapabilities& caps = system_cpu_capabilities(); | CPUCapabilities& caps = system_cpu_capabilities(); | ||||
| return caps.sse && caps.sse2 && caps.sse3 && caps.ssse3 && caps.sse41 && caps.avx && caps.f16c && caps.avx2 && caps.fma3 && caps.bmi1 && caps.bmi2; | return DebugFlags().cpu.avx2 && | ||||
| caps.sse && caps.sse2 && caps.sse3 && caps.ssse3 && caps.sse41 && caps.avx && caps.f16c && caps.avx2 && caps.fma3 && caps.bmi1 && caps.bmi2; | |||||
| } | } | ||||
| #else | #else | ||||
| bool system_cpu_support_sse2() | bool system_cpu_support_sse2() | ||||
| { | { | ||||
| return false; | return false; | ||||
| } | } | ||||
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